1. Field of the Invention
The present invention relates in general to a spread spectrum clock generator, phased-lock loop arrangement of an SSCG, a method of generating a spread spectrum clock signal and a modulation controller of a SSCG.
2. Description of the Related Art
A phase locked-loop (PLL) may be an indispensable circuit in digital systems. Technology developments have led to high-speed, highly integrated digital systems and PLLs, which in one respect may be the source or cause of electromagnetic interference (EMI). If a high frequency signal has energy exceeding a given reference value, EMI occurs and may cause malfunction of peripheral electronic circuits, for example, semiconductor integrated circuits.
However, a spread spectrum clock generator (SSCG) may be used to reduce EMI. In general in a SSCG, a reference signal having substantial energy, e.g., power, at a specific frequency may be modulated into a spread spectrum clock (SSC) signal having a given bandwidth and energy at a frequency less than that of the reference signal. For example, if the frequency of the reference signal is 1 MHz, the reference signal may be modulated into a signal having a frequency band of 0.99 MHz to 1.01 MHz in a given repetition cycle.
The clock frequency of the PLL is not fixed to a reference frequency and may vary in given range of frequencies. As a result, EMI may be avoided by dispersing energy of the specific frequency, resulting in a signal having lower energy spread or a lower range of frequencies. The SSCG thus modulates the clock frequency of the PLL in a relatively small range, thereby reducing the power margin and hence EMI.
FIGS. 1A through 1F are graphs illustrating reference frequency variations of a prior art PLL output signal and a PLL output signal generated by a prior art spread spectrum clock generator (SSCG). FIGS. 1A-1C are directed to signals formed where a SSCG is not used, whereas FIGS. 1D-1F are directed to signals where an SSCG is used.
The graph of FIG. 1A illustrates a clock signal having a constant frequency without using the SSCG and the graph of FIG. 1B shows a frequency spectrum having an energy of the reference frequency (1 MHz of FIG. 1) which is over a given threshold energy P0 that generates EMI. FIG. 1C is a graph illustrating temporal frequency variation of the PLL output signal, which as shown has a constant reference frequency.
FIG. 1D is a graph illustrating a clock signal having a variable frequency generated by the SSCG and the graph of FIG. 1E shows a frequency spectrum that is dispersed around the reference frequency with the energy below the given threshold energy P0. FIG. 1F is a graph illustrating the temporal frequency variation of the output signal, which may vary from 0.99 MHz to 1.01 MHz about the 1 MHz reference frequency, for example
FIG. 2 is a block diagram of a prior art SSCG that adjusts a modulation rate using a dual-loop. In the SSCG using a direct modulation method, a clock modulation rate depends on the gain of a voltage controlled oscillator (VCO) and the size of a modulation charge pump directly applied to a VCO control node. Since the gain of the VCO and the size of the modulation charge pump may vary according to process-voltage-temperature (PVT) conditions or characteristics, a SSCG modulation rate thus varies with the PVT. A substantially small modulation rate results in a small spread spectrum effect, whereas a substantially large modulation rate adversely affects system operation.
For the prior art SSC signal generated using direct modulation, the size of the charge pump is manually adjusted, or the voltage of the VCO control node is adjusted using a dual-loop in order to correct the variation in modulation rate due to the PVT.
Referring now to FIG. 2, there is shown a prior art SSCG 10 which may include a dual-loop (PLL), a master loop 20 and a slave loop 40. The master loop 20 may include a first phase comparator and filter 22 which filters and compares the phase of an input signal F_IN (reference frequency) to a first feedback signal in order to generate a first output signal. The slave loop 40 includes include a second phase comparator and filter 42 which filters and compares the phases of the first feedback signal and a second feedback signal from a comparator 46 in order to generate a second output signal. The second output signal is a voltage V_MVLL is input to a waveform generator 44 to generate a modulation voltage V_MOD, which is scaled at scalar 50 and added to the first output signal at adder 24 to generate a VCO control voltage that is input to a voltage controlled oscillator (VCO) 25. The VCO 25 generates the SSC signal based on the VCO control voltage. The SSC signal is used by a main divider 26 to generate the first feedback signal that serves as an input to both the first phase comparator and filter 22 and second phase comparator and filter 42
Since the prior art SSCG 10 thus senses the voltage of a VCO control node 45 using the dual-loop, the SSCG 10 requires a sufficient modulation voltage V_MOD to satisfy the input sensitivity of the comparator 46. The V_MOD voltage should thus be scaled before being input to the adder 24. However, since the modulation rate is generally several percentage points, and the VCO control voltage generated in a master loop 20 is several volts, a voltage scalar should be precisely operated in a unit of mV.
Also, the master loop 20 and slave loop 40 occupy a substantially large surface area due to their respective filters. Since the waveform generator 44 receives the voltage V_MVLL through the filters, the waveform generator 44 changes a ripple of the voltage V_MVLL into the ripple of the voltage V_MOD, which is a random modulation, thereby reducing a spread spectrum effect.